Other EMF Frequency Synthesize Pages

• Low Noise
• L.O. Upgrade (Military)
• L Band (Military / Commercial)
• Low Noise (Communications)
• C Band (Commercial - Weather)

Synthesizer Techniques

General
      A synthesizer is an oscillator in a phase locked loop where the ratio, N, of the output frequency to the reference frequency can be changed. The oscillator can be any of the various types; VCO, VCXO, CRO, DRO or YIG, depending on the frequency range, phase noise, bandwidth, spurious response, switching speed, and cost requirements of the synthesizer. The oscillator's output now has the benefits of phase locking such as improved stability and phase noise, along with the added benefit of "tunable" frequency. The frequency tunes in steps equal to the reference frequency or the reference frequency divided by some integer M. Therefore the output frequency is

      There are many ways to implement the N and M factors. Typically the step size equals the reference frequency (M = 1) or the reference is divided digitally to get the step size desired, and the phase comparison is done at that frequency, called phase detector frequency, F_pd.

      The oscillator can be digitally divided down to F_pd, or a step diode can be used to "multiply" F_pd to the oscillator frequency and a sampling phase detector can be used. The oscillator could also be down-converted and then digitally divided to F_pd, or the oscillator could be locked at a lower frequency and then multiplied up to the desired output frequency. In practice synthesizers often incorporate several of these methods to achieve the desired performance.

Noise Considerations
    Loop Bandwidth
      Within the bandwidth of the phase locked loop the output phase noise of a synthesizer is related to the reference by:

      Typically the crystal oscillator used for the reference has very good close in phase noise which then levels off near 10 KHz offset at around -150 dBc/Hz. The free running oscillator to be phase locked typically has much higher close in noise but continues down to less than -150 dBc beyond 1 MHz. At some offset the reference noise multiplied up to the output frequency, becomes higher than the oscillator's free running noise. This is the point where the designer wants to set the loop bandwidth. Inside the loop the oscillator noise is improved by the reference, yet outside the loop it is not degraded by the reference.

      Example: Determine loop bandwidth. A 10 MHz reference has phase noise of -145 dBc/Hz at 1 KHz offset and levels off at -150 dBc at 10 KHz. The 1 GHz oscillator has noise of -65 dBc at 1 KHz, -100 dBc at 10 KHz, -120 dBc at 100 KHz and -140 dBc at 1 MHz. (Figure 1 - below.) The reference multiplied up to 1 GHz (N=100, 20 log N = 40 dB) would have phase noise of -145 + 40 = -105 dBc at 1 KHz, and -150 + 40 = -110 dBc at 10 KHz and beyond. If the loop bandwidth is set at 30 KHz, the best noise at each offset is obtained, ie. reference noise of -105 dBc at 1 KHz and -110 at 10 KHz, and oscillator noise of -120 dBc at 100 KHz and -140 at 1 MHz. In practice an additional 3 dB is usually added for circuit noise inside the loop. Another consideration when setting the loop bandwidth is the spurious specification. The wider the loop the less the reference spur will be suppressed at the output.

      The designer must often accept the higher noise floor of ECL and IC dividers for their higher frequency operation, lower power consumption, smaller size and lower cost. Then up/down-conversion, multiple loops and other schemes must often be employed to achieve the desired noise and spurious performance.

Figure 1 (left)

Noise Floor
      As mentioned above, within the loop bandwidth the output phase noise of a synthesizer is related to the reference by:

      therefore lower output frequency or higher reference frequency mean improved phase noise. If the reference is divided to a smaller step size its phase noise decreases by the same 20 log N factor. In theory this means that changing the step size does not affect the phase noise of the synthesizer. In practice however there is the problem of component noise floors. Phase detectors and digital dividers have characteristic noise floors that range from below -165 dBc/Hz for TTL devices to around -150dBc/Hz for ECL, and as high as -130 for some IC phase locked loop devices. (FIG.2  - Below) As the reference is divided down the noise cannot go lower than this floor, so only part of the 20 log N improvement occurs. However, when it is then multiplied back up to the output frequency, the full degradation occurs. This problem typically appears with digital dividers and small step sizes.

      Example: Calculate the effect of noise floor for a 1 GHz oscillator with a 100 MHz reference. The reference has phase noise of -135 dBc/Hz @ 1 KHz offset. N = 10, 20 log N = 20 dB. Locking directly would give phase noise at the output of -135 + 20 = -115 dBc/Hz @ 1 KHz. For a step size of 10 MHz the reference is divided using a TTL divider with a floor of -165 dBc/Hz. At F_pd the noise is

Figure 2 (left)

-135 - 20 = -155 dBc. Multipliying from F_pd to 1 GHz, N=100, 20 log N = 40 dB and the noise is -155 + 40 = -115 dBc. Nothing is lost due to noise floor. Now say a 1 MHz step size is required. The reference is divided by 100, 20 log N = 40 dB, noise at F_pd = -135 - 40 = -175 dB, but this cannot be achieved because the noise floor of the device is only -165 dB. Then it is multiplied back up, N = 1000, 20 log N = 60 dB, and at the output phase noise is -165 + 60 = -105 dBc. The noise is 10 dB worse. For a 100 KHz step size the noise will be degraded another 20 dB to -165 + 80 = -85 dBc. In the same example using an integrated PLL with a floor of -140 dBc, for a 10 MHz step size, phase noise at F_pd is -140 instead of -145 and at the output it is, -140 + 40 = -100 dBc/Hz. The noise is already 15 db worse for the 10 Mhz step size. To maintain good noise performance with small step size it is possible to down-convert the oscillator thereby keeping N low and avoiding the noise floor.

Direct Digital Synthesis
      This is a relatively new type of synthesizer where the output is constructed from a sine lookup table and a digital-to-analog converter. A typical DDS might have a maximum output frequency of 40 MHz and a frequency resolution as fine as .002 Hz. Frequency changes occur in one clock cycle, and phase is continuous. The main problem with using a DDS is the high spurious output level, typically -50 dBc. It is possible to reduce this problem by up-converting the DDS output and then dividing it back down. This method will add considerable complexity and cost to the synthesizer. The DDS output can be used directly, or it can be used as a variable reference in another phase locked loop. DDS can be a valuable tool for the synthesizer designer.